1. Field of the Invention
The present invention relates to an electronic parts packaging structure and a method of manufacturing the same and, more particularly, an electronic parts packaging structure having a package structure in which electronic parts such as a semiconductor device (chip), and the like are mounted in an inside of a wiring substrate to attain a reduction in thickness and a method of manufacturing the same.
2. Description of the Related Art
Improvements in the functions of the electronic parts are facilitated recently. The LSI (Large Scale Integrated Circuit) technology as the key technology makes progress steadily toward a higher speed and a larger capacity of the data transmission. Also, the LSI packaging technology is progressing year by year, and a large number of LSIs can be mounted in a narrow space at a high density.
In reply to the request for the higher density, the multi-chip package (semiconductor device) in which a plurality of semiconductor chips are stacked and mounted three-dimensionally on the wiring substrate has been developed. As an example, there is the semiconductor device having such a structure that a plurality of semiconductor chips are mounted three-dimensionally on the wiring substrate in a state that they are buried in the insulating film and a plurality of semiconductor chips are connected mutually via via holes and wiring patterns formed in the insulating film (Patent Literatures 1 to 5, for example).    [Patent Literature 1] Patent Application Publication (KOKAI) 2001-196525    [Patent Literature 2] Patent Application Publication (KOKAI) 2001-177045    [Patent Literature 3] Patent Application Publication (KOKAI) 2000-323645    [Patent Literature 4] Patent Application Publication (KOKAI) 2005-217225    [Patent Literature 5] Patent Application Publication (KOKAI) 2005-209689
Meanwhile, in case the insulating film for coating the semiconductor chip is formed of a resin, the semiconductor chips and the wiring (metal films), whose coefficients of thermal expansion are different from that of the resin film, exist in the resin film. Therefore, the semiconductor device is warped easily due to a thermal stress caused by a difference between these coefficients of thermal expansion when the resin film is thermally treated and formed. As a result, it is possible that such defects are produced that such warp interferes with handling of the semiconductor device in post treatment, the reliability of connection is decreased upon mounting the semiconductor device on the mounting substrate (mother board), etc.
In above Patent Literatures 1 to 5, the structure in which the semiconductor chips are buried and mounted in the insulating film (resin film) are set forth respectively, nevertheless no consideration is given to the warp of the semiconductor device caused due to the above thermal stress.